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Register-Based Testing

Contents are extracted from the Advanced UVM sessions by Verification Academy.

Register-based analysis components

The register model mirror value is used by analysis components

  • Scoreboards to check current DUT configuration
    • Where this may affect the checking algorithm
  • Functional coverage monitors
    • What is the configuration at a triggered sample?

Analysis components access physical registers passively (using the backdoor accesses):

  • No ability to drive the bus
  • Backdoor read() or peek() accesses

They look up the register model values directly

  • spi_rm.ctrl.get_mirrored_value(data);
  • spi_rm.ctrl.value or spi_rm.ctrl.get(data);

Register Scoreboard guidelines

Scoreboard needs a handle to the register model

Scoreboard accesses register values from model

Scoreboard checks DUT register contents

  • Compare observed data vs. register model contents
  • Compare DUT contents vs. expected
    • via peek access to the DUT

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Scoreboard checking

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Functional coverage monitors

The register model has built-in functional coverage

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A custom functional coverage monitor can be defined to sample based on significant events

  • Interrupts
  • Writes to certain trigger registers

Register Assistant generates ‘intelligent’ register access covergroup

  • Included in the register package code

Functional coverage monitor example

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Coding guideline

Allow the ability to override covergroup when necessary (uvm_object is overridden)

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Monitor with Wrapped covergroup

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Modeling memory

The register model provides access to memory region

  • mem.read()/mem.write() to location x in memory y

  • The memory location address offset is calculated

    system-verilog
    mem.read(status, offset_addr, data, ...);
    mem.write(status, offset_addr, data, ...);

The model does not shadow memory regions

  • DUT memories are usually modelled separately
  • Maintaining a memory shadow is expensive
  • No set() / get() functions available

Memory accesses can support bursts

  • mem.burst_read()
  • mem.burst_write()

Example memory based sequence

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Built-in Memory sequences

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Register Summary

Register block contains

  • Register model
    • Fields
  • Address Map
  • Sub-blocks

Register analysis components have register block pointer

  • Access via get() or backdoor read/peek
  • Use model.reg.value directly

Wrap covergroups to increase flexibility

Use built-in test sequences for sanity checking

  • Registers and memories

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